University of Delaware:

A Cadence University Program Member

CVORG and other groups in the Electrical & Computer Engineering Department at the University of Delaware use Cadence software. This page is dedicated to the use of this software by students and faculity to produce custom IC’s, SiP, Digital IC’s, Verifications and SPB(PCB).

Research Use

  • Dr. Michael Haney’s Group
    The Cadence Package frequently used in our group is the Envisia Silicon Ensemble for placement and routing. The purpose is to evaluate new methods of System level Interconnect Prediction, more specifically, Intra-Chip Global interconnects. We use stochastic methods to estimate interconnect densities in high speed digital systems (mostly microprocessors and systems-on-a-chip) and make predictions about the future technology generations in absence of netlist information. The accuracy of stochastic prediction methods needs to be validated against actual place and route data that provides pointers to how the techniques can be improved. There can be two ways of doing it. Either generate bench mark netlists that capture the interconnect topology of current and then place and route them under relaxed timing, routing area, delay in critical nets and signal noise constraints. Or, we can start with vhdl/verilog netlists (freeware) for SPARC, RISC and other generic micro-architectures. The layout generation is not necessary as we only require interconnect data statistics, obtained from the placement and routing process. The floor plan is defined to mimic current practices in microprocessor physical design. Placement and routing data allows for extraction such important parameters as the local and global rent exponents for sub-blocks/blocks, average wirelength, terminal distributions, multi-terminal nets, routing area, metallization layer environments etc. These are then compared with the data generated by stochastic techniques to evaluate and accordingly modify, to use better methods.
  • Dr. Fouad Kiamilev’s Group
    The research group directed by Dr. Fouad Kiamilev at the University of Delaware focuses on the development of novel electronics hardware for a variety of applications. This includes custom mixed-signal integrated circuit design, fabrication, and test, and printed circuit board design and fabrication as well as system demonstrations. One of our focuses has been the development of systems which use free-space optical links and fiber optic links. Additionally, we develop circuits for use with optical (and other) sensors and optical beam steering devices such as MEMS mirrors and spatial light modulators. In our research projects we use the Cadence IC design tools for schematics, simulation, layout, and verification. We also use the Cadence PCB tools for printed circuit board design and verification.

Class Use

  • CPEG460/660: Introduction to VLSI Systems
    Study of CMOS VLSI devices, circuits and systems implemented in VLSI. CAD tools that used in design of VLSI circuits. Topics include the performance and limitations of VLSI systems, low level circuit design and system design with the primary emphasis on digital systems. Major chip design project required

Local Resources

Offsite Resources


Site last updated March 26, 2017. Kiamilev (kiamilev AT UDel Edu).

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If you have any questions about this site or use of CADENCE software at University of Delaware, send me an email. I am responsible for the UDEL CADENCE University program. You are welcome to visit my research group site here.
Professor Fouad Kiamilev
ECE Department at the University of Delaware